Four Layers of Encryption. Per Message. Every Time.

SimpleGo implements the complete SimpleX cryptographic stack natively in C on bare-metal microcontrollers — four nested cryptographic envelopes per message, routed through TLS 1.3 transport via two relay servers. The same architecture that the Trail of Bits audit found cryptographically sound, now running on a 240 MHz processor with 512KB of RAM.

Why Four Layers Matter

Most messaging protocols use two encryption layers: end-to-end encryption plus TLS transport. SimpleX wraps every message in four nested cryptographic envelopes and routes it through TLS 1.3 transport via two relay servers. Each layer defends against a different attacker with a different capability.

4 Encryption Layers — Per Message
e2e

Layer 1 — Double Ratchet End-to-End

The innermost envelope. X3DH key agreement, then the Double Ratchet derives unique keys for every single message. Even if one key is compromised, all other messages remain secure. Since v5.6, augmented with hybrid post-quantum crypto (CRYSTALS-Kyber + Streamlined NTRU Prime).

X3DH + X25519 Perfect Forward Secrecy Post-Quantum Kyber + NTRU
Defends against: Server compromise, network surveillance, MITM — even if every relay is hostile, content stays encrypted.
▼ wrapped in ▼
s2d

Layer 2 — Sender → Destination Relay

The already-encrypted message gets a second envelope addressed to the recipient's destination relay. This hides the message metadata (queue address, notification flags) from the forwarding relay. Even if TLS is broken, queue correlation is impossible.

X25519 NaCl Cryptobox Per-Queue Unique Keys
Defends against: Forwarding relay seeing message metadata — it only sees an opaque blob destined for the next hop.
▼ wrapped in ▼
d2r

Layer 3 — Destination Relay → Recipient

The destination server re-encrypts the message with a recipient-specific key before delivery. Incoming and outgoing ciphertext is completely different — a network observer cannot correlate what goes in with what comes out.

XSalsa20-Poly1305 Server-Side Re-Encryption
Defends against: Traffic analysis at the destination relay — incoming and outgoing streams are cryptographically unlinkable.
▼ wrapped in ▼
f2d

Layer 4 — Forwarding → Destination (Onion Layer)

The outermost application envelope. Before reaching the destination, the message routes through a forwarding relay chosen by the sender — a 2-hop onion routing protocol inspired by Tor. This layer ensures no repeated identifiers or ciphertext between the two relay hops, preventing traffic correlation even if TLS is compromised on both hops simultaneously.

2-Hop Onion Routing Since v5.8 / Default v6.0 IP Address Protection
Defends against: IP correlation — the forwarding relay knows the sender but not the destination; the destination relay knows the queue but not the sender. Neither sees both.
Transport Security — TLS 1.3 Tunnels
TUNNEL 1
TLS 1.3
Client → Forwarding Relay
TUNNEL 2
TLS 1.3
Forwarding → Destination
TUNNEL 3
TLS 1.3
Destination → Recipient
Fixed-Size Padding

Every message padded to fixed block sizes at each layer. A one-word reply is indistinguishable from a 10,000-character essay.

The Result

4 encryption layers · TLS 1.3 transport · 2 relay servers · neither relay knows both sender and recipient · no other messaging system does this.

Quantum-Resistant by Design

Quantum computers will eventually break the elliptic curve cryptography that protects today's communications. SimpleGo is built to survive that transition — not as an afterthought, but as a core architectural requirement.

The Quantum Threat

A sufficiently capable quantum computer running Shor's algorithm would break RSA, Diffie-Hellman, and elliptic curve cryptography in hours. While such machines don't yet exist, intelligence agencies are already executing "harvest now, decrypt later" campaigns — recording encrypted traffic today to decrypt it once quantum computers become available.

This is not a theoretical concern. NIST spent eight years evaluating 82 candidate algorithms before finalizing FIPS 203 (ML-KEM) in August 2024 as the primary post-quantum key encapsulation standard. The algorithm, derived from CRYSTALS-Kyber, is designed to resist attacks from both classical and quantum computers.

SimpleX Protocol already implements hybrid post-quantum key exchange since version 5.6, combining CRYSTALS-Kyber with Streamlined NTRU Prime — two mathematically independent post-quantum algorithms from different design families. If either algorithm is broken, the other still provides security.

ML-KEM on ESP32

A peer-reviewed implementation of CRYSTALS-Kyber on ESP32 (Segatz & Hammer, KTH Stockholm, 2025) demonstrates that post-quantum cryptography is fully viable on SimpleGo's hardware platform.

By leveraging the ESP32-S3's dual-core architecture and hardware SHA/AES accelerators, the researchers achieved significant performance improvements over naive implementations — proving that a 240 MHz microcontroller can perform post-quantum key exchange in real time.

1.84×
Encapsulation speedup
with dual-core + HW accel
1.72×
Key generation speedup
with dual-core + HW accel
SimpleGo PQC Roadmap
Hybrid ML-KEM-768 + X25519 key exchange
Dual PQC: CRYSTALS-Kyber + NTRU Prime (matching SimpleX)
ESP32-S3 dual-core optimized implementation
Hardware-accelerated SHA-256 and AES operations
ML-DSA-65 (CRYSTALS-Dilithium) signatures (Tier 2/3)

The Protocol With No User Identifiers

SimpleX is the only messaging protocol that uses no persistent user identity of any kind — no phone numbers, no usernames, no public keys as identifiers. This isn't a feature. It's the fundamental architecture.

Unidirectional Message Queues

Communication doesn't happen through "accounts" or "contacts." Each conversation uses a pair of one-way message queues. The sender's queue and the recipient's queue are on different servers, operated by different parties. No single server knows both sides of a conversation.

No Contact Graph

Even with full access to all relay servers, no adversary can construct a social graph — the map of who communicates with whom. Other protocols protect message content but leak this metadata. As former NSA General Counsel Stewart Baker stated: metadata tells you everything about somebody's life.

Disposable by Design

A SimpleGo device has no phone number, no IMEI, no Apple or Google account. It generates ephemeral cryptographic identities that exist only for the duration of a conversation. Power off the device, destroy it, buy another — your communication pattern leaves no persistent trace.

Protocol Comparison — Every Major Messenger

Protocol / AppUser IdentifierEncryption LayersE2E Default?Contact Graph Visible?Forward SecrecyPost-Quantum
SMS / RCSPhone number + IMSI0 (plaintext)NoYes — carrier + authoritiesNoNo
TelegramPhone number1 (MTProto 2.0) — E2E optionalNo — server-side defaultYes — Telegram serversNo (server chats)No
iMessageApple ID + phone number2 (custom + TLS)YesYes — Apple serversPartialYes (PQ3, since iOS 17.4)
WhatsAppPhone number2 (Signal Protocol + Noise Pipes)YesYes — Meta serversYesNo
SignalPhone number2 (Double Ratchet + TLS)YesPartially — Signal servers via SGXYesYes (PQXDH, since Sept 2023)
ThreemaThreema ID (random)2 (NaCl + TLS)YesYes — Threema serversPartial (Ibex)No
WireEmail or phone2 (Proteus/MLS + TLS)YesYes — Wire serversYesNo
Matrix / ElementUsername@server2 (Vodozemac/Megolm + TLS)Yes (rooms)Yes — homeserverPartial (Megolm)No
SessionSession ID (public key)2 (custom + onion routing)YesReduced — onion routedNo (no ratchet)No
BriarPublic key (Tor)2 (Bramble + Tor/direct)YesReduced — P2P via TorYesNo
SimpleX / SimpleGoNone — zero identifiers4 (2 E2E + 2-3 transport)YesNo — to nobodyYesYes (Kyber + NTRU)

Signal pioneered post-quantum protection with PQXDH in September 2023. Apple followed with PQ3 in iMessage. SimpleX uses a hybrid approach combining CRYSTALS-Kyber and Streamlined NTRU Prime since v5.6 — the only protocol with dual post-quantum algorithms. All other major messengers remain vulnerable to harvest-now-decrypt-later quantum attacks.

Native C on Bare Metal

SimpleGo is the world's first implementation of the SimpleX Messaging Protocol outside of the original Haskell codebase. Every cryptographic primitive runs natively in C — no interpreters, no virtual machines, no garbage collectors between your keys and the hardware.

Key Agreement
X3DH + X25519

Extended Triple Diffie-Hellman establishes shared secrets between contacts. Curve25519 provides 128-bit security equivalent. mbedTLS hardware-accelerated where available.

Ratcheting
Double Ratchet

Symmetric-key ratchet combined with Diffie-Hellman ratchet. New keys derived for every message. HKDF-SHA256 for key derivation. Persistent ratchet state stored in NVS flash with encryption.

Symmetric Encryption
XSalsa20-Poly1305

NaCl cryptobox for per-queue and server encryption layers. 256-bit keys, 192-bit nonces, Poly1305 authentication. SimpleX uses a non-standard nonce construction that SimpleGo matches exactly.

Transport
TLS 1.3 via mbedTLS

Full TLS 1.3 handshake with SMP relay servers. Certificate pinning on first contact. mbedTLS provides hardware acceleration on ESP32-S3 for AES and SHA operations.

Key Storage
NVS + Secure Element

Ratchet state persisted after every encrypt/decrypt operation. NVS flash encryption with AES-256-XTS via eFuse keys. Hardware secure elements (Tier 2/3) provide tamper-resistant root-of-trust.

Memory Architecture
SRAM / PSRAM Split

TLS and cryptographic operations in 512KB internal SRAM (DMA-compatible). Contact data and ratchet state arrays in 8MB PSRAM. 128 concurrent contacts supported with zero-latency switching.

Defense in Depth — Beyond the Protocol

The four per-message encryption layers protect data in transit. But what about data at rest on the device? SimpleGo implements multiple independent hardware security domains that protect keys, chat history, and device integrity even if the device is physically seized.

1
In Transit

4 per-message encryption layers + TLS 1.3 transport

2
At Rest — Flash

eFuse-derived AES-256-XTS encryption on internal flash memory

3
At Rest — Storage

AES-256 encrypted chat history on removable SD card

4
Root of Trust

Hardware secure elements + tamper detection + secure boot chain

Processor Security — Chip by Chip
ESP32
S3

Espressif ESP32-S3

MODEL 1 — MAKER WIFI MODULE IN MODEL 2 & 3

Dual-core Xtensa LX7 at 240 MHz with 512KB internal SRAM and 8MB PSRAM. In Model 1, this is the main processor running the complete SimpleX protocol stack. In Models 2 and 3, the ESP32-C6 serves as a dedicated WiFi module while the STM32 handles all cryptographic operations.

Hardware Security Features
eFuse Key Storage — One-time programmable fuses physically burn encryption keys into silicon. Once written, keys cannot be read back by software, only used by the hardware AES engine. Irreversible.
Flash Encryption — AES-256-XTS encrypts the entire flash partition including NVS (Non-Volatile Storage) where ratchet states and contact keys are stored. The encryption key lives only in eFuse — extracting the flash chip yields only ciphertext.
Secure Boot v2 — RSA-3072 or ECDSA signature verification ensures only authenticated firmware runs. The signing key hash is burned into eFuse. Modified firmware is rejected at boot.
Hardware TRNG — True Random Number Generator based on physical noise sources (thermal noise, jitter). All cryptographic key generation uses hardware randomness, not pseudo-random algorithms.
AES/SHA Hardware Accelerators — Dedicated silicon for AES and SHA-256 operations. TLS handshakes and NaCl encryption run on hardware, not in software — faster and resistant to timing side-channels.
What This Means

Even in Model 1 — the €100-200 maker edition — every ratchet state, every contact key, every piece of persistent data is encrypted at the hardware level with a key that cannot be extracted from the chip. Desoldering the flash memory gives an attacker nothing but encrypted bytes.

The eFuse mechanism is physically destructive: writing a bit literally blows a microscopic fuse inside the silicon. There is no "unburning" an eFuse. This is not software protection that can be bypassed with a debugger — it is a permanent physical change to the chip.

ESP32
P4

Espressif ESP32-P4

MODEL 1 PRO UPGRADE PATH

Espressif's high-performance RISC-V processor: dual-core at 400 MHz (HP core) plus a low-power core at 40 MHz, with 768KB internal SRAM. The P4 has no integrated WiFi or Bluetooth — it requires an ESP32-C6 companion chip as a dedicated radio, creating the same hardware-enforced crypto/radio separation as the STM32-based models while staying entirely within the Espressif ecosystem and ESP-IDF toolchain.

Hardware Security Features
Crypto/Radio Separation — Like the STM32 models, the P4 handles all cryptographic operations while the ESP32-C6 is a pure radio. No shared memory, no shared bus. The radio never touches plaintext or key material. This is the fundamental architecture upgrade over the ESP32-S3.
eFuse Key Storage — Same one-time-programmable fuse technology as the S3, physically burning encryption keys into silicon. Once written, the hardware AES engine uses them but software cannot read them back.
Flash Encryption + Secure Boot — AES-256-XTS flash encryption and RSA/ECDSA secure boot chain, matching the S3's capabilities but running on the significantly faster RISC-V architecture.
Hardware Crypto Accelerators — Dedicated AES, SHA, RSA, and ECC acceleration silicon. Post-quantum key exchange benefits significantly from the 400 MHz RISC-V cores — nearly 2× the clock speed of the ESP32-S3's Xtensa cores.
MIPI-DSI Display Interface — Native high-resolution display support enables premium screen options without the display controller overhead of the S3's SPI-based approach. Better displays with lower CPU load.
Why the P4 Matters

The ESP32-P4 bridges the gap between Model 1 and Model 2. It gives you the crypto/radio hardware separation of the STM32 architecture without leaving the Espressif ecosystem. Same ESP-IDF toolchain, same C codebase, same development workflow — but with the architectural security upgrade that matters most: the radio chip never sees your keys.

At 400 MHz with 768KB SRAM, the P4 also has headroom for post-quantum cryptography operations that push the S3 to its limits. ML-KEM key encapsulation and Double Ratchet with PQC augmentation run noticeably faster.

Architecture comparison:
ESP32-S3 — WiFi + Crypto on same chip (Model 1)
ESP32-P4 — Crypto only + ESP32-C6 radio (Model 1 Pro)
STM32 — Crypto + TrustZone + ESP32-C6 radio (Model 2/3)
STM32
U585

STMicroelectronics STM32U585

MODEL 2 — SHIELD

ARM Cortex-M33 at 160 MHz with TrustZone hardware isolation. In Model 2, this processor handles all cryptographic operations and protocol logic while the ESP32-C6 is reduced to a pure WiFi radio. The STM32U5 series was specifically designed by ST for security-critical applications — IoT, payment terminals, and industrial control.

Security Architecture
ARM TrustZone — Hardware-enforced isolation splits the processor into a Secure World and a Normal World. Cryptographic keys and operations run in the Secure World, completely invisible to application code. A compromised application cannot access key material — the CPU itself enforces the boundary.
OTFDEC — On-The-Fly Decryption engine. External memory (OSPI flash) is transparently decrypted during read access using AES-128. The CPU sees plaintext, but the physical memory contains only ciphertext. No performance penalty.
AES/PKA/HASH Hardware — Dedicated cryptographic accelerators: AES-128/256, public key accelerator for RSA/ECC, SHA-256 hardware engine. All crypto runs on dedicated silicon, not CPU instructions.
RDP Level 2 — Readout Protection at maximum level permanently disables JTAG/SWD debug access and all flash readback. Irreversible — once set, the only way to "reset" is to erase the entire chip. An attacker with physical access and debug probes gets nothing.
Tamper Detection Pins — Dedicated hardware pins that monitor for physical intrusion. Opening the case, removing a screw, breaking a seal — any of these can trigger an immediate key wipe before an attacker reaches the circuit board.
Secure Boot + Secure Firmware Update — Root-of-trust boot chain verifies firmware integrity from first instruction. Over-the-air firmware updates are cryptographically signed and verified before installation.
Architecture Split
The STM32 + ESP32-C6 architecture creates a hardware-enforced separation:
STM32U585 — All crypto, all keys, all protocol logic, TrustZone-isolated secure operations
ESP32-C6 — WiFi radio only. Receives encrypted data via SPI/UART, passes it to STM32. Never touches plaintext. Never stores keys.

This is the same architectural principle that makes the Purism Librem 5 noteworthy: separating the radio from the crypto engine. But where the Librem 5 uses a Linux-based application processor, SimpleGo uses bare-metal firmware with TrustZone — a fundamentally smaller and more auditable attack surface.

STM32
U5A9

STMicroelectronics STM32U5A9

MODEL 3 — VAULT

The same ARM Cortex-M33 core as the U585, but with 2.5MB Flash, 2.5MB SRAM, and a GPU-capable LTDC display controller for driving premium AMOLED screens. Every security feature of the U585 is present, plus additional capabilities that enable the full "Vault" experience.

The Model 3 uses the same STM32 + ESP32-C6 architecture split as Model 2, but adds the triple-vendor secure element array and active tamper detection with battery-backed RTC tamper monitoring — the device detects intrusion attempts even when powered off.

All STM32U585 Features 2.5MB SRAM LTDC Display Controller Battery-Backed Tamper Triple-Vendor SE Array
Triple-Vendor Secure Elements — Model 3
Vendor 1
Microchip ATECC608B
CC EAL5+ Certified

Secure key storage, ECDH key agreement, ECDSA signing, hardware RNG. 16 key slots with individual access policies. The industry standard for IoT secure elements.

Vendor 2
Infineon OPTIGA Trust M
CC EAL6+ Certified

Advanced shielding against physical side-channel attacks, fault injection protection, and secure monotonic counters. German engineering from the world's largest secure element manufacturer.

Vendor 3
NXP SE050
CC EAL6+ Certified

IoT-optimized secure element with native NIST P-256/384, Ed25519, AES, and RSA-4096 support. Pre-provisioned root of trust. Active shield mesh against probing attacks.

Why three vendors? In 2024, NinjaLab researchers demonstrated the "Eucleak" attack — a side-channel vulnerability in Infineon SLE78 secure elements used in YubiKeys, passports, and crypto wallets worldwide. The flaw existed for 14 years in a CC EAL5+-certified chip. A single-vendor SE strategy means a single point of failure. Triple-vendor means: if one manufacturer's silicon has an undiscovered vulnerability, the other two still protect your keys.

No device in any category — consumer, military, or prototype — was found to use secure elements from three different manufacturers. The closest is the Keystone 3 Pro hardware wallet with three SE chips from two vendors. Triple-vendor secure elements appear to be an entirely novel concept in hardware security design.

Encrypted Storage — SD Card

Chat History Encryption

All chat messages stored on the removable microSD card are encrypted with AES-256 before writing. The encryption key is derived from keys stored in the secure element (Model 2/3) or eFuse-protected NVS (Model 1). Removing the SD card and reading it on another device yields only encrypted data.

The SD card is the only component that stores message history. Internal flash stores only ratchet states and contact keys — never message content. This separation means: destroy the SD card and all message history is gone. The device can continue operating with existing contacts but no chat history.

Key Separation

Different key material protects different domains. The SD card encryption key, the NVS flash encryption key, and the per-contact ratchet keys are all independent. Compromising one domain does not give access to any other. This is the same principle used in military Red/Black hardware separation — but applied at the key management level.

SD Chat history encryption key
NVS Flash encryption via eFuse AES-256-XTS
E2E Per-contact Double Ratchet state
SE Secure element master keys (Model 2/3)
Tamper Detection — Physical Security
Model 1 — Maker
Software Wipe

Panic button triggers secure erase of all keys and ratchet states from NVS. Flash encryption via eFuse protects data at rest. No hardware tamper sensors — security relies on the eFuse-protected flash encryption and the physical security of the 3D-printed or user-built enclosure.

Model 2 — Shield
Hardware Tamper Pins

STM32U585 tamper detection pins connected to case intrusion switches. Opening the CNC-machined aluminum enclosure triggers an interrupt that wipes all key material from RAM and NVS before an attacker can probe the circuit board. RDP Level 2 permanently disables debug access.

Model 3 — Vault
Active Tamper + Battery Backup

Everything from Model 2, plus battery-backed RTC tamper monitoring — detects intrusion even when the device is powered off. Multiple tamper zones (case, PCB, display). Triple SE array ensures key material is distributed: even extracting one chip leaves the key reconstruction incomplete.

Security FeatureModel 1 — MakerModel 1 ProModel 2 — ShieldModel 3 — Vault
Main ProcessorESP32-S3ESP32-P4STM32U585STM32U5A9
ArchitectureXtensa LX7 240 MHzRISC-V 400 MHzCortex-M33 160 MHzCortex-M33 160 MHz
Internal SRAM512 KB768 KB786 KB2.5 MB
WiFi ModuleIntegratedESP32-C6 (radio only)ESP32-C6 (radio only)ESP32-C6 (radio only)
Crypto/Radio Separation✓ Hardware✓ Hardware✓ Hardware
ARM TrustZone✗ (RISC-V)
Flash EncryptionAES-256-XTS (eFuse)AES-256-XTS (eFuse)AES-256-XTS + OTFDECAES-256-XTS + OTFDEC
Secure BootRSA-3072 / ECDSARSA-3072 / ECDSASTM32 Secure BootSTM32 Secure Boot
Debug ProtectioneFuse JTAG disableeFuse JTAG disableRDP Level 2 (permanent)RDP Level 2 (permanent)
Hardware TRNG
AES/SHA Accelerator✓ + RSA/ECC✓ + PKA✓ + PKA
Display InterfaceSPI (2.8" TFT)MIPI-DSISPI / ParallelLTDC (AMOLED)
Secure ElementsNoneOptional 1 SE1-2 SE3 SE (3 vendors)
Tamper DetectionSoftware wipeSoftware wipeHardware pinsActive + battery-backed
SD Card EncryptionAES-256AES-256AES-256 (SE-derived key)AES-256 (SE-derived key)
Enclosure3D-printed / DIY3D-printed / DIYCNC aluminumCNC aluminum + laser engraving
Price Range€100 — €500€500 — €1,500€1,500 — €15,000€1,000+

All four models implement the same SimpleX Protocol with the same four per-message encryption layers. The difference is in how the device protects the keys that make that encryption work. Model 1 relies on ESP32-S3's built-in security (eFuse, flash encryption, secure boot). Model 1 Pro upgrades to the ESP32-P4, adding hardware crypto/radio separation while staying in the Espressif ecosystem. Model 2 adds ARM TrustZone, STM32 tamper pins, and external secure elements. Model 3 adds triple-vendor SE redundancy and active tamper detection that works even when powered off.

No Device Achieves More Than Three of Six

After researching more than 70 devices across consumer, military, criminal, and DIY domains, we found that no existing device — or even published concept — combines more than three of SimpleGo's six security properties.

Device / CategoryType4× Enc.Bare MetalNo BasebandNo IdentityMulti-Vendor SEOpen SourceScore
SimpleGo (Tier 3)Dedicated HW6/6
Open-Source Mesh Devices
Meshtastic (T-Deck)LoRa Mesh3/6
MeshCoreLoRa Mesh3/6
Reticulum / RNodeLoRa Stack3/6
ArmachatLoRa Mesh3/6
Hardened Smartphones
Bittium Tough Mobile 2CFinland, ~€2,000~0.5/6
GrapheneOS / Pixel$499–$1,799~0.5/6
Purism Librem 5 USAUSA, $1,999~~1/6
NitroPhone (Nitrokey)Germany, €630–€1,500~0.5/6
Necunos NC_1Finland, €1,199~2.5/6
KATIM PhoneUAE, ~$800–$2,0000/6
Sirin Labs SolarinDefunct, was $14,0000/6
Military / Government
Sectra Tiger/S 7401Sweden, NATO SECRET1/6
GD Sectéra vIPerUSA, NSA Type 1N/A1/6
GSMK CryptoPhoneBerlin, dual-algo~0.5/6
R&S TopSec MobileGermany, BSI VS-NfD1/6
Boeing BlackUSA, classified0/6
goTenna Pro X2USA, ~$1,000–$2,0002/6
Criminal Encrypted Networks (all shut down)
EncroChatShut down 2020, 60K users~0.5/6
Sky ECCShut down 2021, 170K users~0.5/6
ANOM (FBI honeypot)Shut down 2021~0.5/6
Phantom SecureShut down 20180/6
GhostShut down 2024~0.5/6
Hardware Wallets (for reference — closest SE architecture)
Keystone 3 Pro3 SEs, 2 vendorsN/A~2.5/6
Coldcard Mk42 SEs, 1 vendorN/A~2.5/6

✓ = fully achieved · ~ = partial · ✗ = not present · N/A = not applicable. The tilde (~) for Bittium indicates three encryption types (disk, VPN, E2E) but these operate at different network layers, not as three per-message cryptographic envelopes. For GrapheneOS, open source is partial because Titan M2 firmware remains proprietary.

The "World's Most Secure Phone" Falls Short

Bittium Tough Mobile 2C

Finland · ~€2,000 · NATO Restricted · NCSA-FI Confidential · FIPS 140-2

The strongest certified smartphone. Dual-boot hardened Android, dedicated secure element, always-on tamper monitoring, privacy mode button, TEMPEST-tested. Achieves three encryption types: disk encryption, VPN tunnel via Bittium Secure Suite, and E2E via Bittium Secure Call. But all three operate at different network stack layers — not as three cryptographic envelopes around each message. Its Qualcomm Snapdragon 670 integrates a standard baseband without physical separation. Proprietary, closed-source firmware. Score: 0.5/6.

Sectra Tiger/S 7401

Sweden · Classified · NATO SECRET · SCIP interoperable · Quantum-resilient

The gold standard for NATO secure mobile communications. Custom-built handset with TEMPEST verification, tamper response, Red/Black hardware separation. Deployed across the majority of European NATO nations and now claims quantum-resilient cryptography. Uses classified algorithms rather than layered commercial crypto. But: proprietary, closed-source, requires cellular baseband, mandatory identity binding. The military's highest-assurance approach and SimpleGo's polar opposite in design philosophy. Score: 1/6.

GSMK CryptoPhone

Berlin · €1,500+ · Dual-algorithm · Baseband Firewall 2.0

The only phone using two symmetric algorithms simultaneously: AES-256 and Twofish as parallel counter-mode stream ciphers with 4096-bit Diffie-Hellman key exchange. Its patented Baseband Firewall 2.0 monitors baseband activity and detects IMSI catchers. Source code available for security review — unique among high-security phones. But: still runs Android, still has a baseband processor (monitored, not eliminated), no secure elements, and dual encryption is not triple-layer per-message. Score: 0.5/6.

The architectural insight: Existing devices cluster in two distant regions. High-assurance military devices (Sectra Tiger, Sectéra vIPer) use classified algorithms with tamper response, TEMPEST shielding, but run on proprietary, closed-source, baseband-equipped platforms with mandatory identity. Open-source mesh devices (Meshtastic, Reticulum) run bare-metal firmware with no baseband and full transparency, but have zero hardware security and basic encryption. SimpleGo occupies the space between these clusters — combining the cryptographic sophistication of the military domain with the openness and baseband elimination of the privacy domain. No other device or published concept exists in this design space.

Audited. Verified. Open.

Trail of Bits
July 2024

The SimpleX SMP protocol underwent a comprehensive cryptographic design review by Trail of Bits — one of the world's leading security audit firms. The review assessed the protocol's security properties and formally verified the queue negotiation protocol. SimpleGo implements this exact protocol specification.

SimpleGo's own codebase is fully open source. Every line of cryptographic code is publicly auditable on GitHub. We plan to commission an independent security audit of the C implementation once the protocol stack is feature-complete.

All source code, protocol documentation, and hardware schematics are published under open-source licenses. Security claims that can't be independently verified are marketing — not engineering.

Explore the Hardware

Three security tiers. Three threat models. One codebase. See the devices that run this cryptographic stack.